www.iterrac.com IT4033D 100-ps dual independent wideband phase delay (advanced information) this is an advanced data sheet . see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4037 rev 0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features the IT4033D is a dual-independent ultra-wideband phase delay fabricated using 1-um hbt gaas technology and is based on ecl topology to guar antee high-speed operat ion. the high output voltage, excellent rise and fall time, and the high ey e diagram quality at data rates to 12.5 gb/s makes the IT4033D suitable for timing adjustment in data and clock distribution at very high speed. complex digital applications benefit from t he IT4033D, including clock data recovery, edge detectors, nrz-to-rz converters, mux/demux, an d data restoration. the device features a dual delay element that provides up to 100-ps delay. delay control can be either differential (using both vcp and vcm) or single-ended (vcm is the active control pad while vcp is shorted to vcref). the control voltage range for the delay in put is from -2.2 v to -3.0 v whether the control is single-ended or differential. the device can delay nrz streams wi th data rates to 12.5 gb/s or a clock signal up to 10.7 ghz. both inputs and output s are dc-coupled. at the input si de, internal 50-ohm resistors avoid the need for external impedance matching terminations. the IT4033D uses scfl i/o levels and is designed so to allow for either single ended or differential data input. ? ultra wideband: up to 12.5 gb/s nrz ? dual independent cores on a single die ? delay adjustment to 100 ps ? 900 mvpp single-ended output ? jitter rms: <1.5 ps device diagram ? output rise time (20% ? 80 %): <21 ps ? output fall time (20% ? 80 %): <18 ps ? 50-ohm matched dc-coupled inputs and outputs ? differential or single ended i/o ? power consumption: 1.6 w (each core)
www.iterrac.com IT4033D 100-ps dual independent wideband phase delay (advanced information) this is an advanced data sheet . see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4037 rev 0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 timing diagram absolute maximum ratings c 150 -65 storage temperature t stg c 125 -15 operating temperature range ? die t a v 0 -5.0 delay control voltage vc v 1.5 -1.5 input voltage level, low level v il v 1.5 -1.5 input voltage level, high level v ih v 0 -5.5 power supply voltage v ee units max. min. parameters/conditions symbol stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v -0.45 dc input voltage (with dc-coupled input) v indc v -0.9 input voltage level, low level (single ended) v il v 0.0 input voltage level, high level (single ended) v ih v -2.2 -2.6 -3.0 delay control voltage vc v -5 power supply voltage v ee c 85 0 operating temperature range ? die t a units max typ. min parameters/conditions symbol recommended operating conditions
www.iterrac.com IT4033D 100-ps dual independent wideband phase delay (advanced information) this is an advanced data sheet . see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4037 rev 0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 ps 250 output delay high-low transition (4) td l ps 250 output delay low-high transition (4) td h ps 17 output fall time (20% ? 80%) t f ps 20 output rise time (20% ? 80%) t r v 1.0 0.9 0.8 data output voltage amplidude (3) v out v -0.45 dc input voltage (with dc-coupled input) (2) v indc v -0.9 input voltage level, low level (single ended) v il v 0.0 input voltage level, high level (single ended) v ih v -5.25 -5.00 -4.5 power supply voltage v ee units max typ min parameters symbol electrical characteristics 1. electrical characteristics at ambient temperature. 2. in case of single- ended input the unused pin has to be tied to vindc. 3. in case of single- ended output, the unused pad must be terminated with 50 ohms to ground. 4. refer to timing diagram. 5. on a 10.7 gb/s prbs pattern. w 3.21 power dissipation p d ma 642 power supply current i ee ps 1.5 rms jitter (5) j rms ps 9 peak-to-peak jitter (5) j p-p ghz 10.7 maximum clock frequency f max db 8 output return loss (up to 15 ghz) s 22 db 24 input return loss (up to 15 ghz) s 11 ps 100 output phase delay adjustment (4) t adj die measurement vee: -5.0 v input data rate:12.5 ghz differential data input: 0/-900 mvpp control voltage: vcp = vcref, vcm = -2.6 v die measurement vee: -5.0 v input clk frequency: 10.7 ghz single-ended clk input: +/-450 mvpp control voltage: vcp = vcref, vcm = -2.2 to -3 .0 v (accumulating) eye diagram performance
www.iterrac.com IT4033D 100-ps dual independent wideband phase delay (advanced information) this is an advanced data sheet . see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4037 rev 0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance (cont.) recommended operational setup die measurement vee: -5.0 v input data rate: 12.5 ghz differential data input: 0/-900 mvpp control voltage: vcp = vcref, vcm = -2.2 to -3 .0 v (accumulating) die measurement vee: -5.0 v input clk frequency: 10.7 ghz single-ended clk input: +/-450 mvpp control voltage: vcp = vcref, vcm = -2.2 to -3 .0 v (accumulating)
www.iterrac.com IT4033D 100-ps dual independent wideband phase delay (advanced information) this is an advanced data sheet . see ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4037 rev 0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended chip mounting pad positions and chip dimensions chip size: 2650 m 10 m x 2650 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m chip size: 2650 m 10 m x 2650 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m
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